Ehsminer: 1Gh/s Asic Scrypt(N) Miner Wolf V1, Development Updates & Preorders - WDRB 41 Louisville News

Ehsminer: 1Gh/s Asic Scrypt(N) Miner Wolf V1, Development Updates & Preorders

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DENVER, CO, September 02, 2014 /24-7PressRelease/ -- The development process of ACSMA (Advanced Configurable Scrypt Mining Architecture).

We are still perfectly on track to release the prototype in less than 25 days from now. It is quite a monumental task to set up a powerful miner which is fast and reliable. We have already passed the biggest hurdles and are well on our way to complete the final tasks within our set time frame. Below are the details of our development:

Functional Simulation:

We studied several approaches to develop a powerful and configurable architecture capable of mining different new SCRYPT oriented virtual currencies. Development started by structuring the architecture in high level language or HLS conversion to obtain RTL code. We obtained for purposes of FPGA prototyping 200K lines of RTL code that were tested in Functional Analysis. This phase was tested with a real cycle simulator (with Real simulation with Questa Advanced Simulator).

The Questa Advanced Simulator is the core simulation and debug engine of the Questa Verification Platform; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs.

After Functional simulation, we have now an idea of resources required to prototype on the FPGA platform. The Scrypt algorithm requires a lot of memory. In a few words the trick is "the faster you can run the algorithm; faster you produce data; more memories you need."

To test architecture like ACSMA we needed a FPGA system with a lot of embedded blocks of memory. In our case 80Mbits were the minimum required and only the Achronix FPGA was fast enough and had that big memory.

Mapping Phase:

The next development phases are physically porting all the RTL code into FPGA logic and memories. After logic synthesis we start to see our developing architecture in terms of logic primitives. The Mapping phase is where all is optimized and connected. Now we have converted all language code into FPGA resources and we need to verify that the conversion process is right and the behavior is equivalent to the functional code we started with.

After Synthesis and mapping is done, the last and more time consuming phase starts:

Placing and Routing Phase:

This phase is iterative as it is very computational intensive, and demands are very limited to the human intervention. Only directives are given at the start of the process of routing to guide the routing algorithm.

After the Prototype is Ready, What is next?

After this phase, everything becomes easy - we'll just do the FPGA/ASIC conversion. The FPGA based design can be converted into an ASIC, which can then be used as a drop-in replacement and this process takes about four working weeks. Production quantities is available in two weeks after conversion approval.

Preorders and Limitation of Stock:

We are happy that we are in our final stage of development and the Prototype will officially be ready in September 26, 2014.

Our stock is limited to 1020 units. Due to this limitation and for whomever wants to secure his place in the queue, they can make their preorder now.

We love crypto.

- Ehsminer Team

EHS Miner designs and produces best-in-class cryptocurrency mining ASIC processors and systems. The company's state-of-the-art design methodologies and advanced architectures enable the delivery of cryptocurrency mining solutions with the highest performance ASICs for the lowest power and die area. EhSMiner boasts a highly experienced engineering team of semiconductor architects and designers who have previously designed some of the world's highest performance FPGAs, GPUs and chipsets for Samsung, Siemens and Intel.

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